1. Field of the Invention
The present invention relates to an electronic device having a nonvolatile memory for storing data to be restored.
2. Description of the Related Art
In electronic devices such as AV amplifiers for amplifying audio signals and outputting them to speakers and personal computers, when power supply to a self device is shut off but then the power source is supplied to the self device, a state of the self device is required to be brought into a state before the power supply is shut off. For this reason, a CPU of an electronic device writes data to be restored (hereinafter, referred to as “restoration data”), which is stored in a volatile memory (for example, an SRAM) provided inside a microcomputer into an EEPROM or the like as a nonvolatile memory before the power supply is shut off. When the power source is again supplied, the CPU of the electronic device again writes (copies) the restoration data stored in the nonvolatile memory into the volatile memory, and returns the self device into the state before the power supply is shut off.
It is also considered that at a moment when the power supply to the electronic device is shut off, the restoration data stored in the volatile memory is written into the nonvolatile memory. Since the nonvolatile memory, however, requires a time for data writing, large-capacity restoration data cannot be written into the nonvolatile memory when the power supply is shut off. For this reason, conventionally, every time when the restoration data stored in the volatile memory changes, the restoration data is written into the nonvolatile memory.
Further, the CPU writes data into the volatile memory according to an application program. Restoration data and data that does not have to be restored (hereinafter, referred to as “restoration unnecessary data”) are occasionally mixed in the data to be written into the volatile memory. In such a case, when the CPU determines whether the data to be written into the volatile memory is restoration data or restoration unnecessary data according to an application program, a structure of the application program becomes complicated. Further, when the application program is corrected according to a specification change, the number of portions to be corrected increases, and erroneous correction is very likely to occur. In order to avoid this, a structure for allowing the CPU to determine whether the data to be written into the volatile memory is the restoration data or the restoration unnecessary data is not provided to the application program, and the application program only allows the CPU to write data into the volatile memory. Another program allows the CPU to monitor whether the restoration data is written into the volatile memory, namely, whether the restoration data stored in the volatile memory changes. Only when the restoration data changes, a process for writing the restoration data into the nonvolatile memory is executed.
A method for detecting whether restoration data changes includes a method for allowing the CPU to read the restoration data stored in the nonvolatile memory and comparing the read restoration data with the restoration data stored in the volatile memory. When the CPU determines that the read restoration data does not match with the restoration data stored in the volatile memory, the CPU detects a change in the restoration data. The nonvolatile memory is, however, connected mostly by a serial interface (particularly, an EEPROM), and thus constant reading of the restoration data from the nonvolatile memory places a burden on the CPU.
Therefore, in order to reduce an access to the nonvolatile memory, a copy of the restoration data written into the nonvolatile memory is written into the volatile memory. FIG. 11 is a diagram illustrating a conventional process for writing data into the volatile memory (SRAM), and a process for writing data into the nonvolatile memory (EEPROM). FIG. 11 illustrates the writing of data into an EEPROM 103 in a form of hardware, but actually a CPU 101 writes data into the EEPROM 103 according to a program (software module) (software process). Regions D01 to D0N of an SRAM 102 are restoration data regions where restoration data is written. Regions C01 to C0N of the SRAM 102 are restoration data copy regions where copy of restoration data is written. The CPU 101 compares restoration data written into the restoration data regions D01 to D0N with copies of restoration data written into the restoration data copy regions C01 to C0N ((1) in FIG. 11). When the CPU 101 determines that the restoration data does not match with the copy of the restoration data, it writes the restoration data into the EEPROM 103 ((2) in FIG. 11). At the same time, the CPU 101 writes the copy of the restoration data into the restoration data copy regions C01 to C0N ((3) in FIG. 11). However, since the copy of the restoration data is written into the SRAM 102, an extra capacity of the SRAM 102 (the volatile memory) is necessary. Particularly when a capacity of the restoration data is large, a writable region of the SRAM 102 (the volatile memory) becomes small, and this is a problem.
As a method for reducing the capacity of the volatile memory where the copy of the restoration data is written, Japanese Patent Application Laid-Open No. 2012-137881 discloses an invention where only a checksum is written into a volatile memory. According to the invention disclosed in Japanese Patent Application Laid-Open No. 2012-137881, a necessary capacity of the volatile memory is greatly reduced, but a capacity for writing of the checksum is necessary. Further, the CPU bears a burden of calculation of the checksum.
Further, since the number of rewriting times is limited in the nonvolatile memory such as an EEPROM, when restoration data that changes frequently is written into the nonvolatile memory at every change time, a life of the nonvolatile memory is shortened. For this reason, the restoration data that changes frequently is written into the nonvolatile memory after some time (a few seconds) passes from the change in some cases (delay writing). Regions D11 to D1n of the SRAM 102 shown in FIG. 11 are delay restoration data regions where restoration data to be delayed and written is written. Regions C11 to C1n of the SRAM 102 are delay restoration data copy regions where a copy of restoration data to be delayed and written is written. The CPU 101 compares the restoration data written into the delay restoration data regions D11 to D1n with the copy of the restoration data written into the delay restoration data copy regions C01 to C0N ((4) in FIG. 11). When the CPU 101 determines that the restoration data does not match with the copy of the restoration data, it starts a timer ((5) in FIG. 11). When the timer overflows ((6) in FIG. 11), the CPU 101 writes the restoration data into the EEPROM 103 ((7) in FIG. 11). At the same time, the CPU 101 writes the copy of the restoration data into the delay restoration data copy regions C11 to C1n ((8) in FIG. 11). As shown in FIG. 11, the conventional process for writing the restoration data into the nonvolatile memory is very complicated.
As described above, there is a problem that the large capacity of the volatile memory is used in order to write restoration data into the nonvolatile memory. Further, it is also a problem that the conventional process for writing the restoration data into the nonvolatile memory is very complicated.